1. Field of the Invention
The invention relates generally to monolithic microwave integrated circuits (MMICs) and, more particularly, to high power multicell transistor configurations therefor.
2. Description of the Related Art
Ground potential continuity in flip-chip monolithic microwave integrated circuits (MMICs) having multicell transistors is critical for preventing the excitation of undesirable slot line modes, which may lead to signal attenuation and degradation. Attempts to achieve ground potential continuity in prior multicell transistor configurations have, however, been unsatisfactory and/or deficient. As shown in FIG. 1, a conventional multicell transistor configuration 10 (each cell being a separate field effect transistor) includes multiple ground straps or bridges 12 for coupling a source interconnect electrode 14 to a pair of ground planes 16 associated with an input coplanar waveguide (CPW) 18. An additional bridge 20 may span an input transmission line 22 of the input CPW 18 to connect the input ground planes 16. Similarly, yet an additional bridge 24 may span an output transmission line 26 of an output CPW 28 to couple a pair of ground planes 30 associated therewith.
Although the ground potential is equalized to a certain extent by the bridges 12, 20, and 24, the conventional multicell transistor 10 does not provide a suitable connection between the input ground planes 16 and the output ground planes 30. Ground potential continuity between the input and output ground planes 16 and 30 may, therefore, be problematic. Furthermore, the ground path (i.e., between the input and output ground planes 16 and 30) is longer than the RF signal path travelling directly through the multicell transistor 10. As a result, an undesirable inductance is effectively added in series with the multicell transistor 10 at microwave frequencies. Still further, the effective signal path for a transistor cell in the center of the multicell transistor 10 differs from that of a transistor cell near the edge of the multicell transistor 10, thereby decreasing or limiting the power combining efficiency of the multicell transistor 10.
The conventional multicell transistor configuration 10 is also undesirable because the fabrication of each bridge 12, 20, and 24 results in a reduction in the thickness of the transmission line over which the bridge crosses. This reduction is particularly critical for the transmission line 26, which typically carries large DC currents. The resulting high DC current density may lead to undesirable electromigration in the transmission line 26.
Attempts to design around the electromigration problem have led to unfavorable consequences. One approach involves widening the transmission line 26 at the crossover point, which modifies the characteristic impedance of the transmission line unless the slot width (shown in FIG. 1 as "w") is increased accordingly. However, the increased slot width renders the multicell transistor more susceptible to loading effects from the substrate of the flip chip module. Alternatively, simply increasing the thickness of the metal layers universally is also undesirable because it requires drastic and potentially unworkable modifications to the fabrication process and overall MMIC design.
The conventional multicell transistor 10 shown in FIG. 1 is still further undesirable because of the configuration of a pair of transmission lines 32 connected to a gate feed electrode 34 for matching the impedances of the input CPW 18 and the gate feed electrode 34. Such a multicell transistor is then said to be prematched, and the power supplied to the gate feed electrode 34 is maximized. The pair of transmission lines 32 have typically been configured to be inductive at microwave frequencies due to the capacitive nature of the gate feed electrode 34. To this end, each transmission line 32 includes a first section 36 extending from the gate feed electrode 34 and a second section 38 orthogonally connected thereto. Each transmission line 32 further includes a third section 40 having one end orthogonally connected to the second section 38 and another end coupled to a respective metal layer 42 spaced from the input ground plane 16 to form a capacitor. Additional bridges 44 couple the input ground planes 16 to exterior ground planes 45 at each of the orthogonal connections to prevent the formation of undesirable slot line modes.
At microwave frequencies, the respective lengths of the sections 36, 38, and 40 provide the inductance necessary for matching the impedances. The capacitors formed by the metal layers 42 and the input ground planes 16 then provide a short to ground for only the higher (i.e., microwave) frequencies.
As shown in FIG. 1, however, the first section 36 of each transmission line 32 extends outwardly from the gate feed electrode 34. As a result, the conventional multicell transistor 10 matches the impedances at the expense of an increase in the overall width of the multicell transistor 10. The increased overall width, in turn, limits the number of transistors that can be placed in a parallel array on the MMIC chip and, therefore, limits the power of the device fabricated therefrom.